The present invention relates to an apparatus for correcting a time base error of a video signal and, more particularly, to an apparatus for correcting a time base error of a reproduced video signal which is reproduced from a recording medium.
In magnetic recording/reproducing apparatuses such as a video tape recorder (VTR) or the like, or in video signal reproducing apparatuses or the like such as a video disc player (VDP) or the like, a time base error occurs in the reproduced video signal due to a relative fluctuation in position between a signal detecting medium such as a magnetic head or a pickup head or the like and a recording medium such as a magnetic tape or a disc or the like. When such a time base error is gentle, it causes a phenomenon of a fluctuation (what is called a jitter) in the reproduced image on the display screen. On the contrary, when the time base rapidly changes (in the case of what is called a skew), it causes a phenomenon of a weave or the like. Thus, there is an essential problem such that stability of the reproduced image is remarkably lost.
As a method of correcting the time base error, there has been hitherto known a time base correcting apparatus as shown in FIG. 1, for example, as is also described in the reference, "VRT Technology, Chapter 6", Broadcasting Technology Books, Vol. 5, Nippon Hoso Shuppan Kyokai.
In FIG. 1, reference numeral 10 denotes an input terminal of a video signal having a time base error, and 20 is an output terminal of the video signal whose time base error was corrected. Numeral 1 denotes an A/D converter to convert the input video signal to a digital signal; 2 is a memory consisting of a RAM or the like; and 4 is a horizontal synchronizing signal separator (H-sync separator). The horizontal sync signal having the time base error which is extracted from the H-sync separator 4 is inputted to a write clock generator (W-CLK generator) 40 and a write address controller (WA controller) 70. The W-CLK generator 40 generates a write clock which is in synchronism with the horizontal sync signal and has the time base error of the input video signal. The WA controller 70 outputs a write address by the write clock.
Therefore, the video signal having the time base error which is inputted form the terminal 10 is sequentially converted into the digital signal by the A/D converter 1 synchronously with the write clock outputted from the W-CLK generator 40. This digital signal is stored into the memory 2 in response to the write address from the WA controller 70.
On the other hand, a stable reference synchronizing signal having no time base error is applied from a terminal 30 and a read clock synchronized with this reference sync signal is generated from a read clock generator (R-CLK generator) 90. A read address controller (RA controller) 80 outputs a read address synchronized with the read clock.
Therefore, the data of the video signal stored in the memory 2 is sequentially read out for every horizontal scan period in response to the read address from the RA controller 80. This readout data is sequentially converted to an analog signal by a D/A converter 3 for converting the data to an analog signal in synchronism with the read clock which is outputted from the R-CLK generator 90. Thus, the stable video signal without any time base error is outputted form the terminal 20.
As will be obvious from the above description of the operation, the performance of the time base correcting apparatus depends on the method of generating the write clock from the W-CLK generator 40. It is a significant factor for the apparatus how to generate the write clock which can accurately follow the time base error of the input video signal.
As described in the above-mentioned reference as well, as a conventional example of the write clock generator 40, a system whereby it is constituted by what is called an automatic frequency controller (AFC) shown in FIG. 2 has been well known.
In FIG. 2, the horizontal sync signal from the H-sync separator 4 is inputted to one end of a phase comparator 43 through a terminal 41. A center frequency of a voltage controlled oscillator (VCO) 45 is set to the same frequency as that of the read clock from the R-CLK generator 90 in FIG. 1. An output of the VCO 45 is frequency divided by a divider 46 and the signal of the same frequency as the horizontal scan frequency of the input video signal is outputted from the divider 46. The horizontal sync signal from the terminal 41 and the output from the divider 46 are phase-compared by the phase comparator 43. A difference voltage corresponding to the phase difference between them is outputted form the phase comparator 43 and supplied as a control voltage of the VCO 45 through a phase compensator 44.
What is called an AFC circuit is constituted by the above-mentioned circuits and the output which follows the time base error of the horizontal sync signal of the input video signal is obtained from the VCO 45 due to the negative feedback control operation of the AFC circuit. This output is outputted from a terminal 42 as the write clock.
In this manner, the write clock is produced on the basis of the horizontal sync signal as a conventional method. As disclosed in the above-mentioned reference, the following method has conventionally been well-known as well. Namely, what is called a burst signal (BS) which is added within the horizontal blanking period is used in place of the horizontal sync signal and a negative feedback loop similar to the above is constituted (this circuit is referred to as an APC circuit (automatic phase controller)). Or, both of the AFC circuit based on the horizontal sync signal and the APC circuit based on the burst signal are used and the write clock synchronized with the video signal is produced.
The conventional well-known method of producing the write clock were described above. However, these conventional methods have the following problem since they are based on the negative feedback control. Namely, in the case where the frequency of the time base error is high or the sudden time base error such as a skew occurs, the follow-up errors of the AFC and APC systems essentially occur, so that the time base error is not corrected but remains. On one hand, to increase the correcting capability, a trial to improve the response speeds of the AFC and APC systems is made. However, this method also causes the following problem. The AFC and APC systems also sensitively respond not only to the noise included in the input video signal but also to the sync information erroneously separated and the lack of sync information, so that the systems are contrarily disturbed or the like and the operation becomes remarkably unstable. Further, the high response speeds of the AFC and APC systems cause the systems to be deviated from the pull-in range when an amount of time base error increases, so that there is a problem such that the time base cannot be corrected any more, or the like.